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gs840fh18/32/36at-8/8.5/10/12 256k x 18, 128k x 32, 128k x 36 4mb sync burst srams 8 ns?12 ns 3.3 v v dd 3.3 v and 2.5 v i/o tqfp commercial temp industrial temp rev: 1.07 10/2004 1/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? flow through mode operation ? 3.3 v +10%/?5% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow floating mode pins ? default to interleaved pipeline mode ? byte write (bw ) and/or global write (gw ) operation ? common data inputs and data outputs ? clock control, registered, address, data, and control ? internal self-timed write cycle ? automatic power-down for portable applications ? jedec-standard 100-lead tqfp ? pb-free 100-lead tqfp package available functional description applications the gs840fh18/32/36a is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous sram with a 2-bit burst address counter. al though of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications ranging from dsp main store to networking chip set support. the gs840fh18/32/36a is available in a jedec-stan dard 100-lead tqfp package. controls addresses, data i/os, chip enables (e 1 , e 2 , e 3 ), address burst control inputs (adsp , adsc , adv ), and write control inputs (bx , bw , gw ) are synchronous and are controlled by a positive-edge-triggered clock input (ck). output enable (g ) and power down control (zz) ar e asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order (lbo ) input. the burst function need not be used . new addresses can be loaded on every cycle with no degradation of chip performance. designing for compatibility the jedec standard for burst rams calls for a ft mode pin option (pin 14 on tqfp). board sites for flow through burst rams should be designed with v ss connected to the ft pin location to ensure the broa dest access to multiple vendor sources. boards designed with ft pin pads tied low may be stuffed with gsi?s pipeline/flow through-configurable burst rams or any vendor?s flow through or configurable burst sram. bumps designed with the ft pin location tied high or floating must employ a non-configurable flow through burst ram, (e.g., gs840fh18/32/36a), to achieve flow through functionality. byte write and global write byte write operation is performed by using byte write enable (bw ) input combined with one or more individual byte write signals (bx ). in addition, global write (gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs840fh18/32/36a operates on a 3.3 v power supply and all inputs/outputs are 3.3 v- and 2.5 v-compatible. separate output power (v ddq ) pins are used to decouple output noise from the internal circuit. parameter synopsis -8 -8.5 -10 -12 flow through 2-1-1-1 t kq tcycle i dd 8 ns 9 ns 210 ma 8.5 ns 10 ns 190 ma 10 ns 12 ns 165 ma 12 ns 15 ns 135 ma
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 2/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840fh18 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b dq b v ss v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b v ss v ddq v ddq v ss dq a dq a v ss v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 nc nc b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 256k x 18 top view dqp a a nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 3/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs84fh32 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 128k x 32 top view dq b nc dq b dq b dq b dq a dq a dq a dq a nc dq c dq c dq c dq d dq d dq d nc dq c nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 4/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840fh36 100- pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 128k x 36 top view dq b dqp b dq b dq b dq b dq a dq a dq a dq a dqp a dq c dq c dq c dq d dq d dq d dqp d dq c dqp c 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 5/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. tqfp pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a i address inputs dq a dq b dq c dq d i/o data input and output pins bw i byte write?writes all enabled bytes; active low b a , b b i byte write enable for dq a , dq b data i/os; active low b c , b d i byte write enable for dq c , dq d data i/os; active low ck i clock input signal; active high gw i global write enable?writes all bytes; active low e 1 , e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active low adsp , adsc i address strobe (processor, cache controller); active low zz i sleep mode control; active high lbo i linear burst order mode; active low v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply nc ? no connect
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 6/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840fh 18/32/36a block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load dq dq register register dq register dq register dq register dq register dq register dq register d q register d q register a0?an lbo adv ck adsc adsp gw bw b a b b b c b d e 1 g zz power down control memory array 36 36 4 a qd e 3 e 2 dqx0?dqx9 note: only x36 version shown for simplicity. 1 0
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 7/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. note: there is a pull-up device on the lbo pin and a pull down device on the zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences notes: 1. all byte outputs are active in read cycles regardle ss of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/o?s remain high-z during all write operations regardless of the state of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on the x32 and x36 versions. mode pin functions mode name pin name state function burst order control lbo l linear burst h or nc interleaved burst power down control zz l or nc active h standby, i dd = i sb byte write truth table function gw bw b a b b b c b d notes read h h x x x x 1 read hlhhhh1 write byte a hl lhhh2, 3 write byte b hlhlhh2, 3 write byte c h l h h l h 2, 3, 4 write byte d hlhhhl2, 3, 4 write all byteshlllll2, 3, 4 write all byteslxxxxx note: the burst counter wraps to initial state on the 5th clock. note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 8/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. synchronous truth table operation address used state diagram key 5 e 1 e 2 adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x x l x x high-z deselect cycle, power down none x l f l x x x high-z deselect cycle, power down none x l f h l x x high-z read cycle, begin burst external r l t l x x x q read cycle, begin burst external r l t h l x f q write cycle, begin burst external w l t h l x t d read cycle, continue burst next cr x x h h l f q read cycle, continue burst next cr h x x h l f q write cycle, continue burst next cw x x h h l t d write cycle, continue burst next cw h x x h l t d read cycle, suspend burst current x x h h h f q read cycle, suspend burst current h x x h h f q write cycle, suspend burst current x x h h h t d write cycle, suspend burst current h x x h h t d notes: 1. x = don?t care, h = high, l = low. 2. e = t (true) if e 2 = 1 and e 3 = 0; e = f (false) if e 2 = 0 or e 3 = 1. 3. w = t (true) and f (false) is defined in the byte write truth table preceding. 4. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 5. all input combinations shown above are tested and supported. in put combinations shown in gray boxes need not be used to accom plish basic synchronous or synchronous burst oper ations and may be avoided for simplicity. 6. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 7. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above.
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 9/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. simplified state diagram first write first read burst write burst read deselect r w cr cw x x wr r wr x x x simple synchronous operation simple burst synchronous operation cr r cw cr cr notes: 1. the diagram shows only supported (tested) synchr onous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assu mes active use of only the enable (e 1, e 2, e 3 ) and write (b a , b b , b c , b d , bw , and gw ) control inputs and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together a ssume active use of only the enable, write, and adsc control inputs and assumes adsp is tied high and adv is tied low.
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 10/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. simplified state diagram with g first write first read burst write burst read deselect r w cr cw x x wr r w r x x x cr r cw cr cr w cw w cw notes: 1. the diagram shows supported (tes ted) synchronous state transit ions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in gray tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time.
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 11/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. notes: 1. unless otherwise noted, all performance specificati ons quoted are evaluated for worst case at both 2.75 v v ddq 2.375 v (i.e., 2.5 v i/o) and 3.6 v v ddq 3.135 v (i.e., 3.3 v i/o) and quoted at whichever condition is worst case. 2. this device features input buffers compat ible with both 3.3 v and 2.5 v i/o drivers. 3. most speed grades and configurations of this device are offer ed in both commercial and industrial temperature ranges. the pa rt number of industrial temperature range versions end t he character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. input under/overshoot voltage must be ?2 v > vi < v dd +2 v with a pulse width not to exceed 20% tkc. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 4.6 v v ddq voltage in v ddq pins ?0.5 to v dd v v ck voltage on clock input pin ?0.5 to 6 v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ?0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/?20 ma i out output current on any i/o pin +/?20 ma p d package power dissipation 1.5 w t stg storage temperature ?55 to 125 o c t bias temperature under bias ?55 to 125 o c recommended oper ating conditions parameter symbol min. typ. max. unit notes supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 2.375 2.5 v dd v1 input high voltage v ih 1.7 ? v dd +0.3 v2 input low voltage v il ?0.3 ? 0.8 v 2 ambient temperature (commercial range versions) t a 02570 c3 ambient temperature (industrial range versions) t a ?40 25 85 c3
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 12/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. note: this parameter is sample tested. notes: 1. junction temperature is a function of sr am power dissipation, package thermal resi stance, mounting board temperature, ambient . temper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87. 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1. capacitance (t a = 25 o c, f = 1 mh z , v dd = 3.3 v) parameter symbol test conditions typ. max. unit control input capacitance c i v dd = 3.3 v 34pf input capacitance c in v in = 0 v 45pf output capacitance c out v out = 0 v 67pf 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd +? 2.0 v 50% v dd v il
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 13/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. notes: 1. include scope and jig capacitance. 2. test conditions as specified wi th output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz , and t ohz . 4. device is deselected as defined by the truth table. ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ?1 ua 1 ua zz input current i inzz v dd v in v ih 0v v in v ih ?1 ua ?1 ua 1 ua 300 ua mode pin input current i inm v dd v in v il 0v v in v il ?300 ua ?1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ?ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh i oh = ?ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = ma ? 0.4 v dq vt = 1.25 v 50 ? 30pf * dq 2.5 v output load 1 output load 2 225 ? 225 ? 5pf * * distributed test jig capacitance
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 14/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. notes: 1. these parameters are sampled and are not 100% tested 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycl e, zz must meet the specified setup a nd hold times as specified above. operating currents parameter test conditions symbol -8 -8.5 -10 -12 unit 0 to 70c -40 to 85c 0 to 70c -40 to 85c 0 to 70c -40 to 85c 0 to 70c -40 to 85c operating current all other inputs v ih o r v il output open i dd flow through 210 220 190 200 165 175 135 145 ma standby current zz v dd ? 0.2 v i sb flow through 20 30 20 30 20 30 20 30 ma deselect current device deselected; all other inputs v ih or v il i dd flow through 40 50 40 50 35 45 35 45 ma ac electrical characteristics parameter symbol -8 -8.5 -10 -12 unit min max min max min max min max flow through clock cycle time tkc 9.0 ? 10.0 ? 10.0 ? 15.0 ? ns clock to output valid tkq ? 8.0 ? 8.5 ? 10 ? 12 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in high-z thz 1 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns g to output valid toe ? 3.2 ? 3.5 ? 3.8 ? 5 ns g to output in low-z tolz 1 0?0?0?0?ns g to output in high-z tohz 1 ? 3.2 ? 3.5 ? 3.8 ? 5 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5?5?5?5?ns zz hold time tzzh 2 1?1?1?1?ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 15/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. flow through mode timing begin read a cont cont write b read c read c+1 read c+2 read c+3 read c cont deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh abc q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) q(c) e2 and e3 only sampled with adsc adsc initiated read deselected with e1 fixed high ck adsp adsc adv a0?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 16/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. sleep mode timing diagram tzzr tzzh tzzs hold setup tkl tkl tkh tkh tkc tkc ck adsp adsc zz
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 17/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840fh18/32/36a output dr iver characteristics -140.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 v out (pull down) vddq - v out (pull up) i out (ma) 3.6v pd hd 3.3v pd hd 3.1v pd hd 3.1v pu hd 3.3v pu hd 3.6v pu hd pull up drivers pull down drivers vddq vout i out vss
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 18/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. tqfp package drawing (package t) d1 d e1 e pin 1 b e c l l1 a2 a1 y notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity 0.10 lead angle 0 ? 7
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 19/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. ordering information fo r gsi synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 status 256k x 18 gs840fh18at-8 flow through tqfp 8 c 256k x 18 gs840fh18at-8.5 flow through tqfp 8.5 c 256k x 18 gs840fh18at-10 flow through tqfp 10 c 256k x 18 gs840fh18at-12 flow through tqfp 12 c 128k x 32 gs840fh32at-8 flow through tqfp 8 c 128k x 32 gs840fh32at-8.5 flow through tqfp 8.5 c 128k x 32 gs840fh32at-10 flow through tqfp 10 c 128k x 32 gs840fh32at-12 flow through tqfp 12 c 128k x 36 gs840fh36at-8 flow through tqfp 8 c 128k x 36 gs840fh36at-8.5 flow through tqfp 8.5 c 128k x 36 gs840fh36at-10 flow through tqfp 10 c 128k x 36 gs840fh36at-12 flow through tqfp 12 c 256k x 18 gs840fh18at-8i flow through tqfp 8 i 256k x 18 gs840fh18at-8.5i flow through tqfp 8.5 i 256k x 18 gs840fh18at-10i flow through tqfp 10 i 256k x 18 gs840fh18at-12i flow through tqfp 12 i 128k x 32 gs840fh32at-8i flow through tqfp 8 i 128k x 32 gs840fh32at-8.5i flow through tqfp 8.5 i 128k x 32 gs840fh32at-10i flow through tqfp 10 i 128k x 32 gs840fh32at-12i flow through tqfp 12 i 128k x 36 GS840FH36AT-8I flow through tqfp 8 i 128k x 36 gs840fh36at-8.5i flow through tqfp 8.5 i 128k x 36 gs840fh36at-10i flow through tqfp 10 i 128k x 36 gs840fh36at-12i flow through tqfp 12 i 256k x 18 gs840fh18agt-8 flow through pb-free tqfp 8 c 256k x 18 gs840fh18agt-8.5 flow through pb-free tqfp 8.5 c 256k x 18 gs840fh18agt-10 flow through pb-free tqfp 10 c 256k x 18 gs840fh18agt-12 flow through pb-free tqfp 12 c 128k x 32 gs840fh32agt-8 flow through pb-free tqfp 8 c 128k x 32 gs840fh32agt-8.5 flow through pb-free tqfp 8.5 c notes: 1. customers requiring delivery in tape and reel should add the c haracter ?t? to the end of the part number. example: gs840fh32a t-7.5t. 2. the speed column indicates the cycle frequency (mhz) of the devic e in pipelined mode and the latency (ns) in flow through mo de. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a variety of different features, on ly some of which are covered in this data sheet. see the gsi technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 20/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. 128k x 32 gs840fh32agt-10 flow through pb-free tqfp 10 c 128k x 32 gs840fh32agt-12 flow through pb-free tqfp 12 c 128k x 36 gs840fh36agt-8 flow through pb-free tqfp 8 c 128k x 36 gs840fh36agt-8.5 flow through pb-free tqfp 8.5 c 128k x 36 gs840fh36agt-10 flow through pb-free tqfp 10 c 128k x 36 gs840fh36agt-12 flow through pb-free tqfp 12 c 256k x 18 gs840fh18agt-8i flow through pb-free tqfp 8 i 256k x 18 gs840fh18agt-8.5i flow through pb-free tqfp 8.5 i 256k x 18 gs840fh18agt-10i flow through pb-free tqfp 10 i 256k x 18 gs840fh18agt-12i flow through pb-free tqfp 12 i 128k x 32 gs840fh32agt-8i flow through pb-free tqfp 8 i 128k x 32 gs840fh32agt-8.5i flow through pb-free tqfp 8.5 i 128k x 32 gs840fh32agt-10i flow through pb-free tqfp 10 i 128k x 32 gs840fh32agt-12i flow through pb-free tqfp 12 i 128k x 36 gs840fh36agt-8i flow through pb-free tqfp 8 i 128k x 36 gs840fh36agt-8.5i flow through pb-free tqfp 8.5 i 128k x 36 gs840fh36agt-10i flow through pb-free tqfp 10 i 128k x 36 gs840fh36agt-12i flow through pb-free tqfp 12 i org part number 1 type package speed 2 (mhz/ns) t a 3 status notes: 1. customers requiring delivery in tape and reel should add the c haracter ?t? to the end of the part number. example: gs840fh32a t-7.5t. 2. the speed column indicates the cycle frequency (mhz) of the devic e in pipelined mode and the latency (ns) in flow through mo de. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a variety of different features, on ly some of which are covered in this data sheet. see the gsi technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
gs840fh18/32/36at-8/8.5/10/12 rev: 1.07 10/2004 21/21 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. 4mb burst datashee t revision history rev. code: old; new types of changes format or content page /revisions;reason 840fh18a_r1_02 content ? updated pin description table 840fh18a_r1_02; 840fh18a_r1_03 content/format ? updated table on page 1 ? updated operating currents table on page 14 ? updated ac electrical char acteristics table on page 14 ? updated ordering information table on page 21 ? updated entire document to comply with technical publications standards 840fh18a_r1_03; 840fh18a_r1_04 content ? reduced i dd by 20 ma in table on page 1 and operating currents table 840fh18a_r1_04; 840fh18a_r1_05 content ? removed 7.5 ns references from entire datasheet 840fh18a_r1_05; 840fh18a_r1_06 content ? updated format ? matched current numbers to nbt parts ? removed preliminary banner 840fh18a_r1_06; 840fh18a_r1_07 content ? added pb-free information to tqfp

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